1. Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method of reducing silicon consumption in the formation of cobalt silicide in the fabrication of integrated circuits.
2. Description of the Prior Art
Cobalt disilicide (CoSi.sub.2) is a preferred salicide technology as CMOS device sizes shrink to 0.18 .mu.m and beyond because of its good performance with small polysilicon and active area line widths. However, CoSi.sub.2 is known to consume more Si than does TiSi.sub.2. This is a drawback for shallow junctions used in future technologies. It is desired to find a process which will form CoSi.sub.2 without increased Si consumption.
U.S. Pat. No. 5,710,438 to Oda et al teaches an ion implant into cobalt before annealing to remove the native oxide film underlying the cobalt layer. U.S. Pat. No. 5,874,342 to Tsai et al teaches using a metal capping layer over cobalt and forming CoSi.sub.2 using two annealing steps. Ions are implanted into the CoSi.sub.2 which is heated again to diffuse the ions into the substrate to form S/D regions. U.S. Pat. No. 5,536,676 to Cheng et al implants ions into polysilicon, then deposits cobalt thereover. The substrate is annealed to form both CoSi and junctions under the polysilicon by diffusion of the implanted ions. U.S. Pat. Nos. 5,824,600 to Byun et al, 5,780,361 to Inoue, and 5,510,295 to Cabral, Jr. et al show various methods of cobalt silicide formation.